PXR40RM Datasheet, PDF (459/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Peripheral Bridge (PBRIDGE)
The modules that are on-platform and those that are off-platform are detailed in Table 15-7.
Table 15-7. On-Platform and Off-Platform Peripherals
On-Platform
Enhanced direct memory access (eDMA)
PBRIDGE A and B
Interrupt controller (INTC)
Error correction status module (ECSM)
System bus crossbar switch (XBAR)
Memory Protection Unit (MPU)
Software Watchdog Timer (SWT)
System Timer Module (STM)
Off-Platform
Deserial serial peripheral interface (DSPI)
Enhanced queued analog-to-digital converter (eQADC)
Enhanced serial communication interface (eSCI)
FlexCAN controller area network
Boot assist module (BAM)
System integration unit (SIU)
Enhanced modular input/output subsystem (eMIOS)
Frequency modulated phase locked loop (FMPLL)
Enhanced time processing unit (eTPU)
External bus interface (EBI)
Flash bus interface unit (FBIU)
FlexRay
Power Management Controller (PMC)
PIT_RTI
Decimation Filters
Temp Sensor
PBRIDGE occupies a 64 MB portion of the address space. A 0.5 MB portion of this space is allocated to
on-platform peripherals. The remaining 63.5 MB is available for off-platform devices. The register maps
of the slave peripherals are located on 16-KB boundaries. Each slave peripheral is allocated one 16-KB
block of the memory map, and is activated by one of the module enables from the PBRIDGE. Up to
thirty-two 16-KB external slave peripherals can be implemented, occupying contiguous blocks of 16 KB.
Two global external slave module enables are available for the remaining 63 MB of address space to allow
for customization and expansion of addressed peripheral devices. In addition, a single non-global module
enable is also asserted whenever any of the 32 non-global module enables is asserted.
PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor or user mode. The
PBRIDGE can block user mode accesses to certain slave peripherals or it can allow the individual slave
peripherals to determine if user mode accesses are allowed. In addition, peripherals can be designated as
write-protected. The PBRIDGE supports the notion of trusted masters for security purposes. Masters can
be individually designated as trusted for reads, trusted for writes, or trusted for both reads and writes, as
well as being forced to look as though all accesses from a master are in user mode privilege level.
PBRIDGE also supports buffered writes, allowing write accesses to be terminated on the system bus in a
single clock cycle, and then subsequently performed on the slave interface. Write buffering is controllable
on a per-peripheral basis. The PBRIDGE implements a two-entry 32-bit write buffer.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
15-15