PXR40RM Datasheet, PDF (556/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Address: EDMA_x_BASE + 0x002C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR}
W ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR}
W ^{15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-20. eDMA Error Register (EDMA_x_ERL)
Table 21-17. EDMA_x_ERL Field Descriptions
Field
0–31
ERRn
eDMA Error n.
0 An error in channel n has not occurred.
1 An error in channel n has occurred.
Description
21.3.2.15 DMA Hardware Request Status (EDMA_A_HRSH, EDMA_x_HRSL)
The EDMA_A_HRSL and EDMA_x_HRSL registers provide a bit map map for the implemented
channels (32 or 64) to show the current hardware request status for each channel. EDMA_A_HRSH maps
to channels 64–32 and EDMA_x_HRSL maps to channels 31-00.
Address: EDMA_A_BASE + 0x0030
Access: User R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS}
W ^{63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS}
W ^{47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-21. EDMA Hardware Request Status Register High (EDMA_A_HRSH)
21-32
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor