PXR40RM Datasheet, PDF (759/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Field
0
OVR
1–15
16
OVFL
17–28
29
UCIN
30
UCOUT
31
FLAG
Table 23-10. EMIOS_CSR[n] Field Descriptions
Description
Overrun Bit. The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set. This
bit can be cleared by clearing the FLAG bit or by software writing a 1.
0 Overrun has not occurred.
1 Overrun has occurred.
Reserved
Overflow Bit. The OVFL bit indicates that an overflow has occurred in the internal counter. This bit must be
cleared by software writing a 1.
0 An overflow has not occurred.
1 An overflow has occurred.
Reserved
Unified Channel Input Pin Bit. The UCIN bit reflects the input pin state after being filtered and synchronized.
Unified Channel Output. The UCOUT bit reflects the output pin state.
FLAG Bit. The FLAG bit is set when an input capture or a match event in the comparators occurred. This bit
must be cleared by software writing a 1.
0 FLAG cleared.
1 FLAG set event has occurred.
Note: emios_flag_out reflects the FLAG bit value. When the DMA bit is set, the FLAG bit can be cleared by
the DMA controller.
23.3.2.9 eMIOS200 Alternate A Register (EMIOS_ALTA[n])
UC[n] base address + 0x0014
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
W
ALTA[0:23]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ALTA[0:23]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-10. eMIOS200 Alternate A Register (EMIOS_ALTA[n])
The EMIOS_ALTA[n] register provides an alternate read-only address to access A2 channel registers in
GPIO, PEC, WPTA, and OPWMT modes. If the EMIOS_CADR[n] register is used with
EMIOS_ALTA[n], both A1 and A2 registers can be accessed in these modes.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-19