PXR40RM Datasheet, PDF (417/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
13.9.2 Machine Check Interrupt (IVOR1)
The Machine Check APU defines a separate set of save/restore registers (MCSRR0/1), a Machine Check
Syndrome register (MCSR) to record the source(s) of machine checks, and a Machine Check Address
register (MCAR) to hold an address associated with a machine check for certain classes of machine checks.
Return from Machine Check instructions (rfmci, se_rfmci) are also provided to support returns using
MCSRR0/1.
The MSR_RI status bit is provided for software use in determining if multiple nested machine check
exceptions have occurred. Software may interrogate the MCSRR1_RI bit to determine if a machine check
occurred during the initial portion of a machine check handler prior to handler code which sets MSR_RI to
‘1’ to indicate that the handler can now tolerate another machine check condition without losing state
necessary for recovery.
13.9.2.1 Machine Check Causes
Machine check causes are divided into different types:
• Error Report Machine Check conditions
• Non-Maskable Interrupt (NMI) machine check exceptions
• Asynchronous machine check exceptions
13.9.2.2 Machine Check Interrupt Actions
Machine Check interrupts for “error report” conditions and NMI are enabled and taken regardless of the
state of MSR_ME. Machine check interrupts due to an “async mchk” syndrome bit being set in MCSR are
only taken when MSR_ME =1. When a Machine Check interrupt is taken, registers are updated as shown
below.
Table 13-17. Machine Check Interrupt - Register Settings
Register
Setting Description
MCSRR0
MCSRR1
MSR
ESR
MCSR
MCAR
Vector
On a best-effort basis, the core sets this to the address of some instruction that was executing or about
to be executing when the machine check condition occurred.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE 0
EE 0
PR 0
FP 0
ME 0
FE0 0
DE 0/—¹
FE1 0
IS 0
DS 0
PMM 0
RI 0
Unchanged
Updated to reflect the source(s) of a machine check. Hardware only sets appropriate bits, no previously
set bits are cleared by hardware.
See
IVPR_0:15 || IVOR1_16:27 || 4b0000
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-29