PXR40RM Datasheet, PDF (1409/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
32.4.3.1 Enabling the TAP Controller
The JTAGC TAP controller is enabled by setting JCOMP to a logic 1 value.
32.4.3.2 Selecting an IEEE 1149.1-2001 Register
Access to the JTAGC data registers is done by loading the instruction register with any of the JTAGC
instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded
in the update-IR state. At this point, all data register access is performed via the select-DR-scan path.
The select-DR-scan path is used to read or write the register data by shifting in the data (LSB first) during
the shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting can be terminated after fetching the required number of bits.
32.4.4 JTAGC Instructions
This section gives an overview of each instruction, refer to the IEEE 1149.1-2001 standard for more
details.
The JTAGC implements the IEEE 1149.1-2001 defined instructions listed in Table 32-3.
Table 32-3. JTAG Instructions
Instruction
IDCODE
SAMPLE/PRELOAD
SAMPLE
EXTEST
ENABLE_CENSOR_CTRL
HIGHZ
CLAMP
ACCESS_AUX_TAP_NPC
ACCESS_AUX_TAP_ONCE
ACCESS_AUX_TAP_eTPU
ACCESS_AUX_TAP_DMA_A
ACCESS_AUX_TAP_NXFR
ACCESS_AUX_TAP_DMA_B
Code[4:0]
00001
00010
00011
00100
00111
01001
01100
10000
10001
10010
10011
10100
10111
Instruction Summary
Selects device identification register for shift
Selects boundary scan register for shifting, sampling, and preloading without
disturbing functional operation
Selects boundary scan register for shifting and sampling without disturbing
functional operation
Selects boundary scan register while applying preloaded values to output
pins and asserting functional reset
Selects CENSOR_CTRL register
Selects bypass register while three-stating all output pins and asserting
functional reset
Selects bypass register while applying preloaded values to output pins and
asserting functional reset
Grants the Nexus port controller (NPC) ownership of the TAP
Grants the Nexus e200z7 core interface (NZ7C3) ownership of the TAP
Grants the Nexus dual-eTPU development interface (NDEDI) ownership of
the TAP
Grants the Nexus crossbar DMA A interface (NXDM) ownership of the TAP
Enables access to the FlexRay Nexus TAP controller
Grants the Nexus crossbar DMA B interface (NXDM) ownership of the TAP
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
32-9