PXR40RM Datasheet, PDF (464/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Memory Protection Unit (MPU)
16.2 Memory Map and Registers
This section provides a detailed description of all MPU registers.
16.2.1 Module Memory Map
The MPU memory map is shown in Table 16-2. The address of each register is given as an offset to the
MPU base address. Registers are listed in address order, identified by complete name and mnemonic, and
list the type of accesses allowed.
The MPU registers can be referenced using 32-bit (word) accesses only. Attempted references using
different access sizes, to undefined (reserved) addresses, or with a non-supported access type (for example,
a write to a read-only register or a read of a write-only register) generate an error termination.
Table 16-2. MPU Memory Map
Offset from
MPU_BASE
(0xFFF1_0000)
Register
Bits Access Reset Value Section/Page
0x0000
MPU_CESR — MPU control/error status register
32
0x0004–0x000F Reserved
0x0010
MPU_EAR0 — MPU error address register, MPU port 32
0
0x0014
MPU_EDR0 — MPU error detail register, MPU port 0 32
0x0018
MPU_EAR1 — MPU error address register, MPU port 32
1
0x001C
MPU_EDR1 — MPU error detail register, MPU port 1 32
0x0020
MPU_EAR2 — MPU error address register, MPU port 32
2
0x0024
MPU_EDR2 — MPU error detail register, MPU port 2 32
0x0028
MPU_EAR3— MPU error address register, MPU port 32
3
0x002C
MPU_EDR3—MPU error detail register, MPU port 3 32
0x0030–0x03FF Reserved
0x0400
MPU_RGD0 — MPU region descriptor 0
32
0x0410
MPU_RGD1 — MPU region descriptor 1
32
0x0420
MPU_RGD2 — MPU region descriptor 2
32
0x0430
MPU_RGD3 — MPU region descriptor 3
32
0x0440
MPU_RGD4 — MPU region descriptor 4
32
0x0450
MPU_RGD5 — MPU region descriptor 5
32
0x0460
MPU_RGD6 — MPU region descriptor 6
32
0x0470
MPU_RGD7 — MPU region descriptor 7
32
0x0480
MPU_RGD8 — MPU region descriptor 8
32
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor