PXR40RM Datasheet, PDF (1029/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 27-24. Clock Divide Factor for Time Stamp (continued)
0b1101
512
0.23
0b1110 - 0b1111
Reserved
—
NOTE
If TBC_CLK_PS is not set to disabled, it must not be changed to any other
value besides disabled. If TBC_CLK_PS is set to disabled it can be changed
to any other value.
27.6.3.3 ADC Time Base Counter Registers (ADC_TBCR)
The ADC Time Base Counter Register (ADC_TBCR) contains the current value of the time base counter.
ADC_TBCR can be accessed by configuration commands sent to CBuffer0 or to CBuffer1. A data write
to ADC_TBCR through a configuration command sent to CBuffer0 will write the same memory location
as when writing to it through a configuration command sent to CBuffer1.
NOTE
Simultaneous write accesses from CBuffer0 and CBuffer1 to ADC_TBCR
are not allowed.
ADC0/1 Register Address: 0x03
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
TBC_VALUE
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-35. ADC Time Base Counter Register (ADC_TBCR)
Table 27-25. ADC_TSCR Field Descriptions
Field
0–15
TBC_VALUE
Description
Time Base Counter value. The TBC_VALUE field contains the current value of the time base counter.
Reading TBC_VALUE returns the current value of time base counter. Writes to TBC_VALUE register load
the written data to the counter. The time base counter counts from 0x0000 to 0xFFFF and wraps when
reaching 0xFFFF.
27.6.3.4 ADC0/1 Gain Calibration Constant Registers (ADC0_GCCR and
ADC1_GCCR)
The ADC0/1 Gain Calibration Constant Register (ADC0/1_GCCR) contains the gain calibration constant
used to fine-tune the ADC0/1 conversion results. Refer to Section 27.7.6.6, ADC Calibration Feature, for
details about the calibration scheme used in the EQADC.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-47