PXR40RM Datasheet, PDF (917/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
details. To work in TSB configuration the DSPI must be in master mode and configured as DSI (DCONF
= 0b01). The TSB allows operating in Continuous and Non Continuous Serial Communication Clock
(controlled by bit CONT_SCKE).
Figure 25-37 shows the signals used in the TSB interface. The SDR and ASDR registers are set to 32 bits
in this configuration, to allow the Micro Second Channel (MSC) feature to be performed.
In the TSB configuration the DSPI manage to send from 4 up to 32 bits data. These bits source data can
be either from the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR), written by the host
software, or from Parallel Input pin states latched into the DSPI DSI Serialization Data Register
(DSPI_SDR).
GPIO or COMMAND
Data Writes
Parallel
Inputs
32 Bit Data
Register
(ASDR)
32 Bit
Serial Data
(SDR)
SOUT (Downstream Frame)
DSI
(Master)
SCK
PCS
Figure 25-37. DSPI usage in the TSB Configuration
The same constraints applied to DSI are valid to TSB, but the frame size and the Delay After Transfer value
(t_DT). The TSB configuration allows from 4 to 32 bits frame size to be used, and t_DT can be programmable
to a minimum of 1xT_SCK, allowing a programmable inter-message gap. See Table 25-12 and Table 25-32
for details on programming the t_DT values.
The time between the negation of the CS at the end of one frame to the assertion of CS at the next frame
is defined by: T_DT = P_DT * DT / f_periph, but delayed until the next active edge of T_SCK. The gap is only be
whole period of TSCK and the PDT and DT fields of the specific DSPI_CTAR0-7 register select the delay
after transfer. Some values will not be possible, see the reference manual for details.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-57