PXR40RM Datasheet, PDF (1280/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
• Number of wait states for a single memory access, and for any beat in a burst access
• Burst enable
• Port size for the external accessed device
See Section 30.3.1.4, EBI Base Registers (EBI_CAL_BR0-3) and Section 30.3.1.5, EBI Option Registers
(EBI_CAL_OR0-3) for a full description of all chip-select attributes.
When no match is found on any of the chip-select banks, the default transfer attributes shown in
Table 30-11 are used.
Table 30-11. Default Attributes for Non-Chip-Select Transfers
CS Attribute
PS
BL
WEBS
TBDIP
BI
SCY
BSCY
AD_MUX
SETA
Default Value
0
0
0
0
1
0
0
0
1
Comment
32-bit port size
burst length is don’t care since burst is disabled
write enables
don’t care since burst is disabled
burst inhibited
don’t care since external D_TA is used
don’t care since external D_TA is used
Address on Data multiplexing (depends on
EBI_MCR[AD_MUX] value)
Select external D_TA to terminate access
30.4.1.5 Burst Support (wrapped only)
The EBI supports burst read accesses of external burstable memory. To enable bursts to a particular
memory region, clear the BI (Burst Inhibit) bit in the appropriate Base Register. External burst lengths of
4 and 8 words are supported. Burst length is configured for each chip select by using the BL bit in the
appropriate Base Register. See Section 30.4.2.5, Burst Transfer for more details on burst operation.
In 16-bit data bus mode (DBM=1 in EBI_MCR), a special 2-beat burst case is supported for reads and
writes for 32-bit non-chip-select accesses only. This is to allow 32-bit coherent accesses to another MCU.
See Section 30.4.2.9, Non-Chip-Select Burst in 16-bit Data Bus Mode.
Bursting of accesses that are not controlled by the chip selects is not supported for any other case besides
the special case of 32-bit accesses in 16-bit data bus mode.
Burst writes are not supported for any other case besides the special case of 32-bit non-chip-select writes
in 16-bit data bus mode. Internal requests to write >32 bits (such as a cache line) externally are broken up
into separate 32-bit or 16-bit external transactions according to the port size. See Section 30.4.2.6, Small
Accesses (Small Port Size and Short Burst Length) for more detail on these cases.
30.4.1.6 Bus Monitor
When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no D_TA assertion is
received within a maximum timeout period for external D_TA accesses. The timeout for the bus monitor
is specified by the BMT field in the EBI_BMCR. Each time a timeout error occurs, the BMTF bit is set in
the EBI_TESR. The timeout period is measured in external bus (D_CLKOUT) cycles. Thus the effective
30-18
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor