PXS20RM Datasheet, PDF (998/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-8. UART receiver scenarios (continued)
Scenario
Responses and suggestions
A STOP request arrives before the reception is
completed.
The request is acknowledged only after the programmed
number of data bytes are received. In other words, the
STOP request is not serviced immediately. In this case,
the software must monitor the UARTSR[TO] field and
move the state machine to IDLE state as appropriate. The
stop request will be serviced only after this is complete.
A parity error occurs during the reception of a byte.
The corresponding UARTSR[PEn] field is set. No interrupt
is generated.
A framing error occurs during the reception of a byte.
• UARTSR[FE] is set.
• If LINIER[FEIE] = 1, an interrupt is generated. This
interrupt is helpful in identifying which byte has the
framing error, since there is only one register bit for
framing errors.
A new byte has been received, but the last received frame
has not been read from the buffer (UARTSR[RMB] has not
yet been cleared by the software)
• An overrun error will occur (UARTSR[BOF] will be set).
• One message will be lost (depending on the setting of
LINCR[RBLM]).
• An interrupt is generated if LINIER[BOIE] is set.
31.10 Memory map and register description
Table 31-9 shows the LINFlexD memory/register map. See the device memory map for the base address.
Table 31-9. LINFlexD memory map
Address offset
Register description
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
LIN control register 1 (LINCR1)
LIN interrupt enable register (LINIER)
LIN status register (LINSR)
LIN error status register (LINESR)
UART mode control register (UARTCR)
UART mode status register (UARTSR)
LIN timeout control status register (LINTCSR)
LIN output compare register (LINOCR)
LIN timeout control register (LINTOCR)
LIN fractional baud rate register (LINFBRR)
LIN integer baud rate register (LINIBRR)
LIN checksum field register (LINCFR)
LIN control register 2 (LINCR2)
Buffer identifier register (BIDR)
Buffer data register least significant (BDRL)
Buffer data register most significant (BDRM)
Identifier filter enable register (IFER)
Location
on page 31-23
on page 31-26
on page 31-28
on page 31-31
on page 31-32
on page 31-35
on page 31-37
on page 31-38
on page 31-39
on page 31-40
on page 31-40
on page 31-41
on page 31-42
on page 31-43
on page 31-44
on page 31-45
on page 31-46
31-22
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor