PXS20RM Datasheet, PDF (307/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
The exception to this rule are the AULB bits in the MGPCR. These update of these bits is only recognized
when the master on that master port runs an IDLE cycle, even though the IP bus cycle to write them will
have long since terminated successfully. If the AULB bits in the MGPCR are written in between two burst
accesses the new AULB encodings will not take effect until an IDLE cycle has been initiated by the master
on that master port.
15.4 Function
This section describes in more detail the functionality of the XBAR.
15.4.1 Arbitration
The XBAR supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a simple
round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave
port.
15.4.1.1 Arbitration During Undefined Length Bursts
Arbitration points during an undefined length burst are defined by the current master’s MGPCR AULB
field setting. When a defined length is imposed on the burst via the AULB bits the undefined length burst
will be treated as a single or series of single back to back fixed length burst accesses.
Example: A master runs an undefined length burst and the AULB bits in the MGPCR indicate arbitration
will occur after the fourth beat of the burst. The master runs two sequential beats and then starts what will
be an 12 beat undefined length burst access to a new address within the same slave port region as the
previous access. The XBAR will not allow an arbitration point until the fourth overall access (second beat
of the second burst). At that point all remaining accesses will be open for arbitration until the master loses
control of the slave port.
Assume the master loses control of the slave port after the fifth beat of the second burst. Once the master
regains control of the slave port no arbitration point will be available until after the master has run four
more beats of its burst. After the fourth beat of the (now continued) burst (ninth beat of the second burst
from the master’s perspective) is taken all beats of the burst will once again be open for arbitration until
the master loses control of the slave port.
Assume the master again loses control of the slave port on the fifth beat of the third (now continued) burst
(10th beat of the second burst from the master’s perspective). Once the master regains control of the slave
port it will be allowed to complete its final two beats of its burst without facing arbitration.
Note that fixed length burst accesses are not affected by the AULB bits. All fixed length burst accesses
lock out arbitration until the last beat of the fixed length burst.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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