PXS20RM Datasheet, PDF (533/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
The ALARM to NORMAL state transition occurs only if all the non-critical faults (including the faults
that have been collected after the entry in the ALARM state) have been cleared (SW or HW recovery)
otherwise the FCCU will remain in the ALARM state.
The FAULT to NORMAL state transition occurs only if all the critical and non-critical faults (including
the faults that have been collected after the entry in the FAULT/ALARM state) have been cleared (SW or
HW recovery) otherwise the FCCU will remain in the FAULT state (if any critical fault is still pending) or
will return in the ALARM state (if any non-critical fault is still pending and the time-out is not elapsed).
In general, no fault nesting is supported except for the non-critical versus critical faults that causes a
ALARM to FAULT state transition. In this case the NCT timer is stopped until the FAULT state is
recovered.
22.7.6 Fault recovery
The following timing diagrams describe the main use cases of the FCCU in terms of fault events and
related recovery.
A typical sequence related to a critical FAULT management, given in Figure 22-28 or Figure 22-29, is
following described:
• Critical fault assertion
• FCCU state transition (automatic): NORMAL  FAULT
— Short ‘functional’ reset
— NMI assertion
— SAFE mode request (delayed)
• Chip mode transition: RUN  RESET  SAFE
• NMI interrupt management
— FAULT recovery (by SW): FCCU state transition FAULT  NORMAL
— Chip mode transition: SAFE  RUN
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
22-33