PXS20RM Datasheet, PDF (557/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
may be attempted. MCR[DONE] goes high no more than Tpsus after MCR[PSUS] is set to a 1. Once
suspended, the FC may only be read. Reads to the block(s) being programmed/erased return indeterminate
data.
The program sequence is resumed by writing a logic 0 to MCR[PSUS]. MCR[EHV] must be set to a 1
before clearing MCR[PSUS] to resume operation. When the operation resumes, the flash module
continues the program sequence from one of a set of predefined points. This may extend the time required
for the program operation.
CAUTION
Repeated suspends at a high frequency may result in the operation timing
out, and the flash module will respond by completing the operation with a
fail code (MCR[PEG] = 0). The minimum time between suspends to ensure
this does not occur is 100 s.
23.1.5.6 C90FL Erase
Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on
any combination of blocks in the Low, Mid or High Address Space, or the shadow block. The erase
sequence is fully automated within the flash. The user only needs to select the blocks to be erased and
initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are selected for
erase during an erase sequence, the blocks are erased sequentially starting with the lowest numbered block
and terminating with the highest. The erase sequence consists of the following sequence of events:
1. Change the value in the MCR[ERS] bit from 0 to a 1.
2. Select the block, or blocks to be erased by writing ones to the appropriate registers in LMS or HBS
registers. If the shadow block is to be erased, this step may be skipped, and LMS and HBS are
ignored. For shadow block erase, see Section 23.1.5.8, C90FL Shadow Block, for more
information.
NOTE
Lock and Select are independent. If a block is selected and locked, no erase
occurs.
3. Write to any address in flash. This is referred to as an erase interlock write. The interlock write
causes the values of SOC specific shadow enable to be captured and causing MCR[PEAS] to be
set/cleared.
4. Write a logic 1 to the MCR[EHV] bit to start an internal erase sequence or skip to step 9 to
terminate.
5. Wait until the MCR[DONE] bit goes high.
6. Confirm MCR[PEG] = 1.
7. Write a logic 0 to the MCR[EHV] bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the MCR[ERS] bit to terminate the erase.
After setting ERS, one write, referred to as an interlock write, must be performed before EHV can be set
to a 1. This interlock causes the values of SOC specific shadow enable to be captured. Data words written
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
23-7