PXS20RM Datasheet, PDF (496/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Table 21-19. Platform RAM syndrome mapping for single-bit correctable errors (continued)
PRESR
0xdd
0xde
0xe1
0xe2
0xe4
0xe7
0xe8
0xeb
0xed
0xee
0xf0
0xf3
0xf5
0xf6
0xf9
0xfa
0xfc
0xff
Data Bit in Error
DATA EVEN BANK[24]
DATA EVEN BANK[25]
DATA EVEN BANK[10]
DATA EVEN BANK[11]
DATA EVEN BANK[12]
DATA EVEN BANK[26]
DATA EVEN BANK[13]
DATA EVEN BANK[27]
DATA EVEN BANK[28]
DATA EVEN BANK[29]
DATA EVEN BANK[14]
DATA EVEN BANK[15]
DATA EVEN BANK[16]
DATA EVEN BANK[17]
DATA EVEN BANK[18]
DATA EVEN BANK[19]
DATA EVEN BANK[20]
DATA EVEN BANK[30]
21.4.2.18 Platform RAM ECC Master Number Register (PREMR)
The PREMR is a 4-bit register for capturing the XBAR bus master number of the last, properly-enabled
ECC event in the platform RAM. Depending on the state of the ECC Configuration Register, an ECC event
in the platform RAM causes the address, attributes and data associated with the access to be loaded into
the PREAR, PRESR, PREMR, PREAT, PREDRL, and PREDRH registers, and the appropriate flag
(R1BC or RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. If no
RAM ECC event is defined to be handled for this module, accesses to this register will terminate with an
error.
See Figure 21-18 and Table 21-20 for the PREMR definition.
Register address: ECSM Base + 0x0066
0
1
2
3
4
5
6
7
R
0
0
0
0
PREMR
W
RESET:
0
0
0
0
-
-
-
-
= Unimplemented
Figure 21-18. Platform RAM ECC Master Number (PREMR) Register
21-22
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor