PXS20RM Datasheet, PDF (618/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
1 = Rx Warning Interrupt enabled
0 = Rx Warning Interrupt disabled
LPB — Loop Back
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an
internal loop back that can be used for self test operation. The bit stream output of the transmitter is
fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes
to the recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting, and treats
its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal
acknowledge bit to ensure proper reception of its own message. Both transmit and receive interrupts
are generated. This bit must be written in Freeze mode only.
1 = Loop Back enabled
0 = Loop Back disabled
SMP — Sampling Mode
This bit defines the sampling mode of CAN bits at the Rx input. This bit must be written in Freeze
mode only.
1 = Three samples are used to determine the value of the received bit: the regular one (sample point)
and 2 preceding samples, a majority rule is used
0 = Just one sample is used to determine the bit value
BOFF_REC — Bus Off Recovery Mode
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering
from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic
recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated
by the user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN
bus, then Bus Off recovery happens as if the BOFF_REC bit had never been asserted. If the negation
occurs after 128 sequences of 11 recessive bits occurred, then FlexCAN will re-synchronize to the bus
by waiting for 11 recessive bits before joining the bus. After negation, the BOFF_REC bit can be
re-asserted again during Bus Off, but it will only be effective the next time the module enters Bus Off.
If BOFF_REC was negated when the module entered Bus Off, asserting it during Bus Off will not be
effective for the current Bus Off recovery.
1 = Automatic recovering from Bus Off state disabled
0 = Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
TSYN — Timer Sync Mode
This bit enables a mechanism that resets the free-running timer each time a message is received in
Message Buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a
special “SYNC” message (i.e., global network time). If the FEN bit in MCR is set (FIFO enabled),
MB8 is used for timer synchronization instead of MB0. This bit must be written in Freeze mode only.
1 = Timer Sync feature enabled
0 = Timer Sync feature disabled
24-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor