PXS20RM Datasheet, PDF (620/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
Base + 0x0008
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000000
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TIMER
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 24-7. Free Running Timer (TIMER)
24.3.4.4 Rx Global Mask (RXGMASK)
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RXGMASK Register to have no effect on the module operation. For MCUs not supporting
individual masks per MB, this register is always effective.
RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14–15, which have individual
mask registers. When the FEN bit in MCR is set (FIFO enabled), the RXGMASK also applies to all
elements of the ID filter table, except elements 6-7, which have individual masks.
Refer to Section 24.4.7, Rx FIFO for important details on usage of RXGMASK on filtering process for Rx
FIFO.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
Base + 0x0010
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R _{MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16}
W
RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0}
W
RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
= Unimplemented or Reserved
Figure 24-8. Rx Global Mask Register (RXGMASK)
MI31–MI0 — Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the
mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
24-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor