PXS20RM Datasheet, PDF (862/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
FLEXRAY
CHI
reg(A)
cfg(A)
PE
channel A
reg(B)
cfg(B)
cCrcInit[A]
channel B
cCrcInit[B]
CA_RX
CA_TX
CA_TR_EN
FlexRay Channel A
FlexRay Bus Driver
Channel A
CB_RX
CB_TX
CB_TR_EN
FLEXRAY
CHI
reg(A)
cfg(A)
reg(B)
cfg(B)
Figure 26-150. Single Channel Device Mode (Channel A)
PE
channel A
cCrcInit[A]
channel B
cCrcInit[B]
CA_RX
CA_TX
CA_TR_EN
FlexRay Bus Driver ^{FlexRay Channel B}
Channel A
Init Value for Frame CRC is cCrcInit[B]
CB_RX
CB_TX
CB_TR_EN
Figure 26-151. Single Channel Device Mode (Channel B)
26.6.11 External Clock Synchronization
The application of the external rate and offset correction is triggered when the application writes to the
EOC_AP and ERC_AP fields in the Protocol Operation Control Register (FR_POCR). The PE applies the
external correction values in the next even-odd cycle pair as shown in Figure 26-152 and Figure 26-153.
26-150
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor