PXS20RM Datasheet, PDF (630/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
Once the MB is activated in the fourth step, it will participate into the arbitration process and eventually
be transmitted according to its priority. At the end of the successful transmission, the value of the Free
Running Timer is written into the Time Stamp field, the Code field in the Control and Status word is
updated, a status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the
corresponding Interrupt Mask Register bit. The new Code field after transmission depends on the code that
was used to activate the MB in step four (see Table 24-4 and Table 24-5 in Section 24.3.2, Message Buffer
Structure). When the Abort feature is enabled (AEN in MCR is asserted), after the Interrupt Flag is asserted
for an MB configured as transmit buffer, the MB is blocked, therefore the CPU is not able to update it until
the Interrupt Flag be negated by CPU. It means that the CPU must clear the corresponding IFLAG before
starting to prepare this MB for a new transmission or reception.
24.4.3 Arbitration process
The arbitration process is an algorithm executed by the MBM that scans the whole MB memory looking
for the highest priority message to be transmitted. All MBs programmed as transmit buffers will be
scanned to find the lowest ID¹ or the lowest MB number or the highest priority, depending on the LBUF
and LPRIO_EN bits on the Control Register. The arbitration process is triggered in the following events:
• During the CRC field of the CAN frame
• During the error delimiter field of the CAN frame
• During Intermission, if the winner MB defined in a previous arbitration was deactivated, or if there
was no MB to transmit, but the CPU wrote to the C/S word of any MB after the previous arbitration
finished
• When MBM is in Idle or Bus Off state and the CPU writes to the C/S word of any MB
• Upon leaving Freeze Mode
When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is transmitted first.
When LBUF and LPRIO_EN are both negated, the MB with the lowest ID is transmitted first but. If LBUF
is negated and LPRIO_EN is asserted, the PRIO bits augment the ID used during the arbitration process.
With this extended ID concept, arbitration is done based on the full 32-bit ID and the PRIO bits define
which MB should be transmitted first, therefore MBs with PRIO = 000 have higher priority. If two or more
MBs have the same priority, the regular ID will determine the priority of transmission. If two or more MBs
have the same priority (3 extra bits) and the same regular ID, the lowest MB will be transmitted first.
Once the highest priority MB is selected, it is transferred to a temporary storage space called Serial
Message Buffer (SMB), which has the same structure as a normal MB but is not user accessible. This
operation is called “move-out” and after it is done, write access to the corresponding MB is blocked (if the
AEN bit in MCR is asserted). The write access is released in the following events:
• After the MB is transmitted
• FlexCAN enters in HALT or BUS OFF
• FlexCAN loses the bus arbitration or there is an error during the transmission
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID
at the same positions they are transmitted in the CAN frame.
24-30
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor