PXS20RM Datasheet, PDF (471/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
20.5.2.13 Usage of Compare Registers
The dual compare registers (COMP1 and COMP2) provide a bidirectional modulo count capability.
The COMP1 register should be set to the desired maximum count value or $FFFF to indicate the maximum
unsigned value prior to roll-over, and the COMP2 register should be set to the minimum count value or
$0000 to indicate the minimum unsigned value prior to roll-under.
If the output mode is set to 0100, the OFLAG will toggle while using alternating compare registers. In this
variable frequency PWM mode, the COMP2 value defines the desired pulse width of the on time, and the
COMP1 register defines the off time. COMP1 is used when OFLAG=0 and COMP2 is used when
OFLAG=1. OFLAG can be forced to a value using CTRL2[FORCE] and CTRL2[VAL].
Use caution when changing COMP1 and COMP2 while the counter is active. If the counter has already
passed the new value, it will count to $FFFF or $0000, roll over, then begin counting toward the new value.
The check is: CNTR = COMPx, not CNTR > COMP1 or CNTR < COMP2.
The use of the CMPLD1 and CMPLD2 registers to preload compare values will help to minimize this
problem.
Clock
CNTR
0
1
2
3
4
5
6
COMP1
COMP2
CMPMODE
OUTMODE
COMP1 match
COMP2 match
OFLAG
3
2
10, use COM1 when counting up, use COMP2 when counting down
0010, set OFLAG on successful compare
successful
compare since
CMPMODE[1]=1
unsuccessful
compare since
CMPMODE[0]=0
Figure 20-30. Compare Register and OFLAG Timing
20.5.2.14 Usage of Compare Load Registers
The CMPLD1, CMPLD2 and CCCTRL registers offer a high degree of flexibility for loading compare
registers with user-defined values on different compare events. To ensure correct functionality while using
these registers we strongly suggest using the following method described in this section.
The purpose of the compare load feature is to allow quicker updating of the compare registers. A compare
register can be updated using interrupts. However, because of the latency between an interrupt event
occurring and the service of that interrupt, there is the possibility that the counter may have already
counted past the new compare value by the time the compare register is updated by the interrupt service
routine. The counter would then continue counting until it rolled over and reached the new compare value.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-29