PXS20RM Datasheet, PDF (945/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

JTAG Controller (JTAGC)
The device identification register is selected for serial data transfer between TDI and TDO when the
IDCODE instruction is active. Entry into the Capture-DR state while the device identification register is
selected loads the IDCODE into the shift register to be shifted out on TDO in the Shift-DR state. No action
occurs in the Update-DR state. The part revision number (PRN) and part identification number (PIN) fields
are system plugs, and the manufacturer identity code (MIC) is a constant value assigned to the
manufacturer by the JEDEC.
The shift register LSB is forced to logic 1 on the rising edge of TCK following entry into the Capture-DR
state. Therefore, the first bit to be shifted out after selecting the IDCODE register is always a logic 1. The
remaining 31 bits are forced to the value of the device identification register on the rising edge of TCK
following entry into the Capture-DR state.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Part Revision Number
Design Center
Part Identification Number
W
RESET:
PRN
DC
PIN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Part Identification Number
Manufacturer Identity Code
1
W
RESET:
PIN (contd.)
000000011101
= Reserved
Figure 29-3. Device Identification Register
PRN — Part Revision Number
Bits [31:28] contain the revision number of the part.
cut1: 0x0
cut2: 0x0
cut3: 0x1
DC — Design Center
Bits [27:22] indicate the design center. The default value is 0x2B.
PIN — Part Identification Number
Bits [21:12] contain the part number of the device.
cut1: 0x2A2
cut2: 0x2A3
cut3: 0x2A3
MIC — Manufacturer Identity Code
Bits [11:1] contain the reduced Joint Electron Device Engineering Council (JEDEC) ID. The default
value is 0x00E.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
29-5