PXS20RM Datasheet, PDF (1176/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Power Management Unit (PMU)
Table 39-3. PMU memory map
Register Name
Reserved
PMU status register (PMUCTRL_STATUS)
PMU control register (PMUCTRL_CTRL)
Reserved
PMU mask fault register (PMUCTRL_MASKF)
PMU fault monitor register (PMUCTRL_FAULT)
PMU interrupt request status register (PMUCTRL_IRQS)
PMU interrupt request enable register (PMUCTRL_IRQE)
Address offset
0x04–0x3F
0x40
0x44
0x49–0x6F
0x70
0x74
0x78
0x7C
39.7.1 PMUCTRL status register (PMUCTRL_STATUS)
Address: Base + 0x40
Location
—
on page 39-6
on page 39-7
—
on page 39-7
on page 39-8
on page 39-9
on page 39-11
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R₁
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₁
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R CTB
0
0
0
0
0
0
0
0
0
0
0
1
1
0
W
Reset ₀
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
Figure 39-3. PMUCTRL status register (PMUCTRL_STATUS)
Field
ENPN
CTB
Table 39-4. PMUCTRL_STATUS field descriptions
Description
External NPN status flag
0 External NPN not detected
1 External NPN detected
Configuration Trace Bits. This field describes the PMU use case after initialization.
00 Reserved (not used on this device)
01 Internal ballast mode without NPN
10 External ballast mode detection with NPN
11 Reserved (not used on this device)
39-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor