PXS20RM Datasheet, PDF (482/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Table 21-9. AHB response and ECC reporting for even and odd ECC
PRAM valid
ECC
Reported ECC
PRAM bus response
AHB HRESP
Even
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
Odd
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Even
x
none
single
multi
x
x
x
none
single
multi
none
single
multi
none
single
multi
Odd
x
x
x
x
none
single
multi
none
none
none
single
single
single
multi
multi
multi
No access, No_error
No_error
Even_single
Even_multi
No_error
Odd_single
Odd_multi
No_error
Even_single
Even_multi
Odd_single
Even_single
Even_multi
Odd_multi
Odd_multi
Even_multi
Even
Odd
xxxx
xxxx
data
xxxx
corrected
xxxx
non-corrected
xxxx
xxxx
data
xxxx
corrected
xxxx
non-corrected
data
data
corrected
data
non-corrected
data
data
corrected
corrected
corrected
non-corrected corrected
data
non-corrected
corrected non-corrected
non-corrected non-corrected
okay
okay
okay
err
okay
okay
err
okay
okay
err
okay
okay
err
err
err
err
As shown in Table 21-9, accesses of only a single memory bank report the ECC from that bank directly.
For accesses involving both banks, the "most severe" ECC response is reported with the even bank taking
priority if the responses are equivalent. This approach also provides improved correction capabilities
compared to the 64-bit ECC implementation.
21.4.2.9 ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches which
are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in
the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the ECSM captures specific information (memory address, attributes
and data, bus master number, etc.) which may be useful for subsequent failure analysis.
See Figure 21-8 and Table 21-10 for the ECC Configuration Register definition.
21-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor