PXS20RM Datasheet, PDF (498/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
21.4.2.20 Platform RAM ECC Data Registers (PREDRL and PREDRH)
These two 32-bit registers contain a 64-bit field, PREDR, for capturing the data associated with the last,
properly-enabled ECC event in the platform RAM. Depending on the state of the ECC Configuration
Register, an ECC event in the platform RAM causes the address, attributes and data associated with the
access to be loaded into the PREAR, PRESR, PREMR, PREAT, PREDRL, and PREDRH registers, and
the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
These registers can only be read from the IPS programming model; any attempted write is ignored. If no
RAM ECC event is defined to be handled for this module, accesses to these registers will terminate with
an error.
Register address: ECSM Base +0x0068
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PREDR[63:48]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PREDR[47:32]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-20. Platform RAM ECC Data High Register (PREDRH)
Register address: ECSM Base +0x006C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PREDR[31:16]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PREDR[15:0]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-21. Platform RAM ECC Data Low Register (PREDRL)
21-24
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor