PXS20RM Datasheet, PDF (1099/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Mode Entry Module (MC_ME)
clock source to power down and updates its availability status bit S_<clock source> of the register to ‘0’.
The following clock sources switched off at this step:
• the system FMPLL
• the secondary FMPLL
This step is executed only after the System clock switching process has completed.
32.4.3.15 Clock Sources (with Dependencies) Switch-Off
Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given
clock source is to be switched off and all clock sources which need this clock source to be on have been
switched off, the MC_ME requests the clock source to power down and updates its availability status bit
S_<clock source> of the register to ‘0’. The following clock sources switched off at this step:
• the 16 MHz internal RC oscillator
• the 4-40 MHz crystal oscillator
This step is executed only after
• the System clock switching process has completed in order not to lose the current system clock
during mode transition
• the Clock Sources (with no Dependencies) Switch-Off process has completed in order to, for
example, prevent unwanted lock transitions
32.4.3.16 Flash Switch-Off
Based on the FLAON bit field of the ME_<current mode>_MC and ME_<target mode>_MC registers, if
the flash is to be put in its low-power or power-down mode, the MC_ME requests the flash to enter the
corresponding power mode and waits for the flash to acknowledge. The exact power mode status of the
flash is updated in the S_FLA bit field of the register. This step is executed only when the Processor and
System Memory Clock Disable process has completed.
32.4.3.17 Current mode update
The current mode status bit field S_CURRENT_MODE of the register is updated with the target mode bit
field TARGET_MODE of the ME_MCTL register when:
• all the updated status bits in the register match the configuration specified in the
ME_<target mode>_MC register
• power sequences are done
• clock disable/enable process is finished
• processor low-power mode (halt/stop) entry and exit processes are finished
NOTE
For cut2/3: SAFE mode entry does not wait for the clock disable/enable
process to finish. It only waits for the ME_GS.S_RC bit to be set. This is to
ensure that the SAFE mode is entered as quickly as possible.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
32-43