PXS20RM Datasheet, PDF (176/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
Table 9-20. NCMR0 field descriptions
Field
CHn
Sampling enable
0 Sampling is disabled for channel n
1 Sampling is enabled for channel n
Description
9.3.11.2 Injected Conversion Mask Register 0 (JCMR0)
Address: Base + 0x0B4
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R _CH1
W5
17
CH1
4
18
CH1
3
19
CH1
2
20
CH1
1
21
CH1
0
22
CH9
23
CH8
24
CH7
25
CH6
26
CH5
27
CH4
28
CH3
29
CH2
30
CH1
31
CH0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-18. Injected Conversion Mask Register 0 (JCMR0)
Table 9-21. JCMR0 field descriptions
Field
CHn
Sampling enable
0 Sampling is disabled for channel n
1 Sampling is enabled for channel n
Description
9.3.12 Power Down Exit Delay Register (PDEDR)
Address: Base + 0x0C8
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
W
PDED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-19. Power-down Exit Delay Register (PDEDR)
Table 9-22. PDEDR field descriptions
Field
Description
PDED The delay between the power-down bit reset and the start of conversion
The power down delay is calculated as: PDED x (1/frequency of ADC clock)
9-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor