PXS20RM Datasheet, PDF (758/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Table 26-37. FR_SYMATOR Field Descriptions
Field
Description
TIMEOUT System Memory Access Time-Out — This value is related to the maximum amount of time to finish a
system bus access in order to ensure correct frame transmission and reception. For a detailed
description see Section 26.6.19.2, System Bus Access Timeout.
26.5.2.33 Sync Frame Counter Register (FR_SFCNTR)
Base + 0x0040
Additional Reset: RUN Command
0
R
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SFEVB
SFEVA
SFODB
SFODA
000000000000000
Figure 26-33. Sync Frame Counter Register (FR_SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the start of the
NIT and before 10 MT after offset correction start.
NOTE
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the CC will not update the
fields SFEVB and SFEVA.
If the application has locked the odd synchronization table at the end of the
static segment of an odd communication cycle, the CC will not update the
values SFODB and SFODA.
Table 26-38. FR_SFCNTR Field Descriptions
Field
Description
SFEVB
SFEVB
SFODB
SFODA
Sync Frames Channel B, even cycle — protocol related variable: size of (vsSyncIdListB for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
Sync Frames Channel A, even cycle — protocol related variable: size of (vsSyncIdListA for even cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
Sync Frames Channel B, odd cycle — protocol related variable: size of (vsSyncIdListB for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
Sync Frames Channel A, odd cycle — protocol related variable: size of (vsSyncIdListA for odd cycle)
This field provides the size of the internal list of frame IDs of received synchronization frames used for
clock synchronization.
26-46
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor