PXS20RM Datasheet, PDF (453/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
Table 20-5. Secondary Count Source Values (continued)
Value
Meaning
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110–11111
Auxiliary input #2 pin
Reserved
Reserved
Reserved
Reserved
Reserved
Counter #0 output
Counter #1 output
Counter #2 output
Counter #3 output
Counter #4 output
Counter #5 output
Reserved
20.4.3.9 Control Register 2 (CTRL2)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10
11
_BASE + $10
Read
Write
OEN
RDN
T
IN-
PUT
VAL
0
FOR
COF
RC
CE
COINIT
SIPS PIPS OPS
MST
R
Reset
00000000000 0
Figure 20-11. Control Register 2 (CTRL2)
12 13 14 15
OUTMODE[3:0]
0000
OEN - Output Enable.
This bit determines the direction of the external pin.
1 = OFLAG output signal will be driven on the external pin. Other timer channels using this external
pin as their input will see the driven value. The polarity of the signal will be determined by the
OPS bit.
0 = The external pin is configured as an input.
RDNT - Redundant Channel Enable.
This bit enables redundant channel checking between adjacent channels (0 and 1, 2 and 3, 4 and 5).
When this bit is clear, the RCF bit in this channel cannot be set. When this bit is set, the RCF bit will
be set by a miscompare between the OFLAG of this channel and the OFLAG of its redundant adjacent
channel which will cause the output of this channel to go inactive (logic 0 prior to consideration of the
OPS bit).
1 = Enable redundant channel checking.
0 = Disable redundant channel checking.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-11