PXS20RM Datasheet, PDF (223/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
Table 11-4. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions
Field
Description
SELDIV
Output Clock Division Select
00 output selected Output Clock without division
01 output selected Output Clock divided by 2
10 output selected Output Clock divided by 4
11 output selected Output Clock divided by 8
SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.
0000 16 MHz int. RC osc.
0001 4-40 MHz crystal osc.
0010 system FMPLL
0011 secondary (80 MHz) FMPLL
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
11.3.1.3 System Clock Select Status Register (CGM_SC_SS)
Address 0xC3FE_0378
Access: User read-only, Supervisor read, Test read
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
SELSTAT
00000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-4. System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
11-9