PXS20RM Datasheet, PDF (730/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Table 26-12. Strobe signal mapping (continued)
SEL
dec hex
14 0xE
Description
receive FIFO almost-full interrupt signals
Channel Type
A
value
15 0xF
B
NOTES:
1 _{Given in PE clock cycles.}
Offset¹
Referenc
e
n.a. RX FIFO
A Almost
Full
Interrupt
RX FIFO
B Almost
Full
Interrupt
26.5.2.7 Message Buffer Data Size Register (FR_MBDSR)
Base + 0x000C
Write: POC:config
0
R0
W
Rese
t
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
MBSEG2DS
MBSEG1DS
000000000000000
Figure 26-7. Message Buffer Data Size Register (FR_MBDSR)
This register defines the size of the message buffer data section for the two message buffer segments in a
number of two-byte entities.
The CC provides two independent segments for the individual message buffers. All individual message
buffers within one segment have to have the same size for the message buffer data section. This size can
be different for the two message buffer segments.
Table 26-13. FR_MBDSR Field Descriptions
Field
Description
MBSEG2DS Message Buffer Segment 2 Data Size — The field defines the size of the message buffer data section
in two-byte entities for message buffers within the second message buffer segment.
MBSEG1DS Message Buffer Segment 1 Data Size — The field defines the size of the message buffer data section
in two-byte entities for message buffers within the first message buffer segment.
26-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor