PXS20RM Datasheet, PDF (914/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
Table 28-2. PRI Values (continued)
PRI
0111
0110
0101
0100
0011
0010
0001
0000
Meaning
Priority 7
Priority 6
Priority 5
Priority 4
Priority 3
Priority 2
Priority 1
Priority 0 - lowest priority
28.4.5 INTC Interrupt Acknowledge Register for Processor 0
(INTC_IACKR_PRC0)
INTC_BASE+0x10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
VTBA_PRC0 (most significant 16 bits)
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20¹ 21 22 23 24 25 26 27 28 29¹ 30 31
R VTBA_PRC0 (least significant 5
INTVEC_PRC0
00
W
bits)
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
NOTES:
1 _{When the INTC_BCR[VTES_PRC0] bit is set, INTVEC_PRC0 is shifted to the left one bit. Bit 29 is read as a ‘0’.}
VTBA_PRC0 is narrowed to 20 bits in width.
Figure 28-4. INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0)
The Interrupt Acknowledge Register for Processor 0 provides a value which can be used to load the
address of an ISR from a vector table. The vector table can be composed of addresses of the ISRs specific
to their respective interrupt vectors.
Also, in software vector mode, the INTC_IACKR_PRC0 has side effects from reads. Therefore, it must
not be read speculatively while in this mode. The side effects are the same regardless of the size of the
read. Reading the INTC_IACKR_PRC0 does not have side effects in hardware vector mode.
VTBA_PRC0[0:20] — Vector Table Base Address for Processor 0.
VTBA_PRC0 can be the base address of a vector table of addresses of ISRs for Processor 0. The
VTBA_PRC0 only uses the leftmost 20 bits when the VTES_PRC0 bit in INTC_BCR is asserted.
INTVEC_PRC0[0:8] — Interrupt Vector for Processor 0.
28-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor