PXS20RM Datasheet, PDF (1330/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
Address: Base + 0x0C40–0x0C4C (4 registers)
0
1
2
3
4
5
R
W
Reset ₀
0
0
0
0
0
6
7
8
9
PPDI[x][15:0]
0
0
0
0
Access: User read-only
10
11
12
13
14
15
0
0
0
0
0
0
16
R
W
Reset ₀
Field
PPDI[x]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PPDI[x+1][15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 47-15. Parallel GPIO Pad Data In Register (PGPDI0–PGPDI3)
Table 47-15. PGPDI0_3 Field Descriptions
Description
Parallel Pad Data In
Read the current pad value.
Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data Input
Registers (GPDI).
The x and bit index define which PPDI register bit is equivalent to which PDI register bit according
to the following equation:
PPDI[x][y] = PDI[(x*16)+y]
47-16
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor