PXS20RM Datasheet, PDF (479/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Field
DP64
ASC[n]
Table 21-5. PLASC field descriptions
Description
64-bit datapath
0 Platform datapath width is 32 bits
1 Platform datapath width is 64 bits
XBAR slave configuration
0 Bus slave to XBAR input port n is absent
1 Bus slave to XBAR input port n is present
21.4.2.5 IPS On-Platform Module Configuration (IOPMC) register
The IOPMC is a 32-bit read-only register identifying the presence or absence of the 32 low-order IPS
peripheral modules connected to the primary slave bus controller. The state of this register is defined by a
module input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 21-5 and Table 21-6 for the IOPMC definition.
Register address: ECSM Base + 0x0008
0
1
2
3
4
5
R
W
RESET: 1
1
0
0
1
0
6
7
8
9
10 11 12 13 14 15
PMC[31:16]
0
0
0
1
0
0
0
0
1
1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PMC[15:0]
W
RESET: 1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 21-5. IPS On-Platform Module Configuration (IOPMC) Register
Table 21-6. IOPMC field descriptions
Field
PMC
Description
IPS Module Configuration
PMC[n] = 0 if an IPS module connection to decoded slot “n” is absent
PMC[n] = 1 if an IPS module connection to decoded slot “n” is present
21.4.2.6 Miscellaneous Reset Status Register (MRSR)
The MRSR contains a bit for each of the reset sources to the device. An asserted bit indicates the last type
of reset that occurred. Only one bit is set at any time in the MRSR, reflecting the cause of the most recent
reset as signalled by device reset input signals. The MRSR can only be read from the IPS programming
model. Any attempted write is ignored.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-5