PXS20RM Datasheet, PDF (405/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Name
SOE
DAE
DOE
NCE
SGE
SBE
DBE
Enhanced Direct Memory Access (eDMA)
Table 19-3. eDMA Error Status (DMAES) field descriptions (continued)
Description
Source Offset Error
Destination Address Error
Destination Offset Error
Nbytes/Citer Configuration Error
Scatter/Gather Configuration Error
Source Bus Error
Destination Bus Error
Value
0 No source offset configuration error.
1 The last recorded error was a configuration error
detected in the TCD.soff field. TCD.soff is
inconsistent with TCD.ssize.
0 No destination address configuration error.
1 The last recorded error was a configuration error
detected in the TCD.daddr field. TCD.daddr is
inconsistent with TCD.dsize.
0 No destination offset configuration error.
1 The last recorded error was a configuration error
detected in the TCD.doff field. TCD.doff is
inconsistent with TCD.dsize.
0 No nbytes/citer configuration error.
1 The last recorded error was a configuration error
detected in the TCD.nbytes or TCD.citer fields.
TCD.nbytes is not a multiple of TCD.ssize and
TCD.dsize, or TCD.citer is equal to zero, or
TCD.citer.e_link is not equal to TCD.biter.e_link.
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error
detected in the TCD.dlast_sga field. This field is
checked at the beginning of a scatter/gather
operation after major loop completion if TCD.e_sg is
enabled. TCD.dlast_sga is not on a 32 byte
boundary.
0 No source bus error.
1 The last recorded error was a bus error on a source
read.
0 No destination bus error.
1 The last recorded error was a bus error on a
destination write.
19.2.1.3 eDMA Enable Request Low (DMAERQL)
The DMAERQL register provides a bit map for the implemented channels to enable the request signal for
each channel. The state of any given channel enable is directly affected by writes to this register; it is also
affected by writes to the DMASERQ and DMACERQ registers. The eDMA{S,C}ERQ registers are
provided so that the request enable for a single channel can easily be modified without the need to perform
a read-modify-write sequence to the DMAERQL register.
Both the eDMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel
service request made explicitly through software or a linked channel request.
See Figure 19-4 and Table 19-4 for the DMAERQL definition.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
19-9