PXS20RM Datasheet, PDF (213/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Architecture
Table 10-1. Clock distribution (continued)
Module name
Clock
Frequency
Supports FM on
PLL
LINFlexD_0
LINFlexD_1
MC_CGM
MC_ME
MC_PCU
MC_RGM
MPU_0
MPU_1
PBRIDGE_0
PBRIDGE_1
PIT
SEMA4_0
SEMA4_1
SIUL (registers)
SIUL (interrupt filters)
SRAM
SSCM
STCU
STM_0
STM_1
SWG
SWT_0
peripheral set 0
 120 MHz
yes
peripheral set 0
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
IRCOSC
16 MHz
—
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
peripheral set 0
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
IRCOSC
16 MHz
—
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
system
 120 MHz
yes
SWG
 20 MHz
yes
IRCOSC
16 MHz
—
SWT_1
IRCOSC
16 MHz
—
WKPU
system
 120 MHz
yes
XBAR_0
system
 120 MHz
yes
XBAR_1
system
 120 MHz
yes
NOTES:
1 _{Selection between FlexCAN clock and XOSC clock is done via the CLK_SRC bit in the FlexCAN_0’s CTRL register.}
2 _{Selection between FlexCAN clock and XOSC clock is done via the CLK_SRC bit in the FlexCAN_1’s CTRL register.}
3 _{Selection between FlexRay clock and XOSC clock is done via the CLKSEL bit in the FlexRay’s FR_MCR register.}
10.3 Detailed module descriptions
Additional details on the clock-related modules on this device are provided in the following chapters:
• Chapter 11, Clock Generation Module (MC_CGM)
• Chapter 12, Clock Monitor Unit (CMU)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
10-3