PXS20RM Datasheet, PDF (306/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Crossbar Switch (XBAR)
MGPCRn
Master General Purpose Control Register n
Addr
$BASE + 0x800 + n*100
Wait State: 0
Access: S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TYPE: r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AULB
TYPE: r
r
r
r
r
r
r
r
r
r
r
r
r rw rw rw
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note: for n = 0 to 7
Figure 15-4. Master General Purpose Control Register n
Table 15-9. Master General Purpose Control Register Descriptions
Name
Bits 0–28
AULB
Description
Setting
Master General Purpose Control Register
Reserved - These bits are reserved for future
expansion. They read as zero and should be written
with zero for upward compatibility.
Arbitrate on Undefined Length Bursts - These bits
are used to select the arbitration policy during
undefined length bursts by this master.
These bits are initialized by hardware reset.
The reset value is 000
NA
000No arbitration will be allowed during an
undefined length burst.
001Arbitration will be allowed at any time
during an undefined length burst.
010Arbitration will be allowed after four
beats of an undefined length burst.
011Arbitration will be allowed after eight
beats of an undefined length burst.
100Arbitration will be allowed after 16
beats of an undefined length burst.
101Reserved
110Reserved
111Reserved
The MGPCR can only be accessed in supervisor mode with 32-bit accesses.
15.3.3 Coherency
Since the content of the registers has a real time effect on the operation of the XBAR it is important for the
user to understand that any register modifications take effect as soon as the register is written. The values
of the registers do not track with slave port related AHB accesses but instead track only with IP bus
accesses.
15-12
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor