PXS20RM Datasheet, PDF (852/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
If there are multiple message buffer with highest priority, the message buffer with the lowest message
buffer number is selected. All message buffer which have the highest priority must have a consistent
channel assignment as specified in Section 26.6.7.2, Message Buffer Channel Assignment Consistency.
Depending on the message buffer channel assignment the same message buffer can be found for both
channel A and channel B. In this case, this message buffer is used as described in Section 26.6.3.1,
Individual Message Buffers.
26.6.7.1 Message Buffer Cycle Counter Filtering
The message buffer cycle counter filter is a value-mask filter defined by the CCFE, CCFMSK, and
CCFVAL fields in the Message Buffer Cycle Counter Filter Registers (FR_MBCCFRn). This filter
determines a set of communication cycles in which the message buffer is considered for message reception
or message transmission. If the cycle counter filter is disabled, i.e. CCFE = 0, this set of cycles consists of
all communication cycles.
If the cycle counter filter of a message buffer does not match a certain communication cycle number, this
message buffer is not considered for message transmission or reception in that communication cycle. In
case of a transmit message buffer assigned to a slot in the static segment, though, this buffer is added to
the matching message buffers to indicate the slot assignment and to trigger the null frame transmission.
The cycle counter filter of a message buffer matches the communication cycle with the number CYCCNT
if at least one of the following conditions evaluates to true:
MBCCFRnCCFE = 0
Eqn. 26-12
CYCCNT & MBCCFRnCCFMSK = MBCCFRnCCFVAL & MBCCFRnCCFMSK
Eqn. 26-13
26.6.7.2 Message Buffer Channel Assignment Consistency
The message buffer channel assignment given by the CHA and CHB bits in the Message Buffer Cycle
Counter Filter Registers (FR_MBCCFRn) defines the channels on which the message buffer will receive
or transmit. The message buffer with number n transmits or receives on channel A if
FR_MBCCFRn[CHA] = 1 and transmits or receives on channel B if FR_MBCCFRn[CHB] = 1.
To ensure correct message buffer operation, all message buffers assigned to the same slot and with the
same priority must have a consistent channel assignment. That means they must be either assigned to one
channel only, or must be assigned to both channels. The behavior of the message buffer search is not
defined, if both types of channel assignments occur for one slot and priority. An inconsistent channel
assignment for message buffer 0 and message buffer 1 is depicted in Figure 26-146.
MB0
MB1
FR_MBFIDR0[FID] = 10 FR_MBCCFR0[CHA] = 1, FR_MBCCFR0[CHB] = 0
FR_MBFIDR1[FID] = 10 FR_MBCCFR1[CHA] = 1, FR_MBCCFR1[CHB] = 1
Figure 26-146. Inconsistent Channel Assignment
single channel assignment
dual channel assignment
26-140
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor