PXS20RM Datasheet, PDF (431/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
eDMA
addr
wdata[31:0]
eDMA engine
hrdata[63:0]
data_path
SRAM
Transfer
Control
Descriptor (TCD)
pmodel_charb
addr_path
c
o
n
t
r
o
l
0
j
j+1
n-1
rdata[31:0]
Peripheral
Bus
AMBA
Bus
hwdata[63:0]
haddr[31:0]
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 19-28. eDMA operation, part 2
Once the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the addr_path logic performs the required updates to certain fields in the channel’s TCD, e.g.,
saddr, daddr, citer. If the outer major iteration count is exhausted, then there are additional operations
which are performed. These include the final address adjustments and reloading of the biter field into the
citer. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of
a new TCD from memory using the scatter/gather address pointer included in the descriptor. The updates
to the TCD memory and the assertion of an interrupt request are shown in Figure 19-29.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
19-35