PXS20RM Datasheet, PDF (208/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
fractional part and thus, two registers (STAW1AR and STAW1BR) are provided. The comparison is done
first for integer part using the threshold values programmed in STAW1AR. If integer part lies in the range,
the fractional part comparison is skipped otherwise it is compared with the values programmed in
STAW1BR. Table 9-48 summarizes this feature for STEP1.
Table 9-48. Algorithm S (STEP1) threshold comparison
STDR2[IDATA]
(integer part)
> STAW1AR[THRH]
< STAW1AR[THRL]
== STAW1AR[THRH]
== STAW1AR[THRL]
STDR2[FDATA]
(fractional part)
Any value
Any value
> STAW1BR[THRH]
< STAW1BR[THRL]
STSR1[ERR_S1]
Set
Set
Set
Set
For Algorithm S STEP2, (VREF/VREF) is measured in order to check the integrity of sampling signal.
For this particular conversion, no higher threshold value is required as the ideal value is 0xFFF. Only lower
threshold value is programmed in STAW2R.
For Algorithm C, a separate register is provided for Step0. In Step0 an offset for other steps is measured.
The converted data is compared with the threshold values provided by STAW5R if STAW4R[AWDE] is
set. For other steps, this offset is subtracted from converted data before performing watchdog checks.
9.4.11.6 Watchdog timer
The watchdog timer is an additional check which monitors the sequence of the self testing algorithm
implemented and also that the algorithm is completed within a safe time period. The Watchdog timers can
be enabled for CPU as well CTU conversions. Each algorithm has a different watchdog timer which runs
independently of the other. The watchdog timer for a particular algorithm can be enabled by setting
STAWnR[WDTE] bit. The safe time value can be programmed in STBRR[WDT] field (default value is
10 ms assuming a 120 MHz clock).
The safe time is measured starting from Step0 of the algorithm (including all normal chain conversions in
between) to the point where Step0 of the same algorithm starts again.
The sequence is as follows:
• Program NCMR0 to select channels to be converted for normal conversion in scan mode
(MODE = 1).
• Select the Self Testing algorithm in STCR3.ALG. By default, all three algorithms are selected i.e.
all algorithms will be executed step by step one after the other.
• Enable self testing channel by setting EN bit in STCR2 register.
• Program safe period value in STBRR.WDT field.
• Enable watchdog timer by setting STAWxR.WDTE bit. Assume setting of WDTE bit to be ‘t0’. (It
is important to do all the programming first and then enable WDTE bit as the safe time check is
also performed between setting of WDTE bit and start of STEP0 to check that algorithm has started
within the safe time).
• Start the normal conversion by setting MCR[NSTART].
9-50
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor