PXS20RM Datasheet, PDF (887/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.6.24.3.4 PE DRAM Error Response after Application Read in POC:default config state
If the module detects an non-corrected memory error during an application triggered read from any PE
DRAM address and the protocol is in the POC:default config state, this is considered as an fatal protocol
error and the module enters the protocol freeze state. This behavior allows for checking the freeze
functionality in case of the detection of non-corrected errors.
26.6.24.3.5 PE DRAM Error Response after Application Read out of POC:default config
If the module detects an non-corrected memory error during an application triggered read from any PE
DRAM address, and the protocol is not in the POC:default config state, this error is not considered as an
fatal error and the protocol state is not changed. This prevents any interference of the running protocol by
PE DRAM error injection reads.
26.6.25 Memory Error Injection
The error injection functionality is used by the application to inject data errors into the memories to trigger
and check the memory error detection functionality.
The error injection is enabled only if the ECC functionality enable bit ECCE in the Module Configuration
Register (FR_MCR) and the error injection enable control bit EIE in the ECC Error Report and Injection
Control Register (FR_EERICR) are set.
The error injection mode is configured by the EIM configuration bit in the ECC Error Report and Injection
Control Register (FR_EERICR).When the error injection is enabled, each write access to the configured
memory location will be distorted.
The injector has the same behavior for FlexRay module memory writes and application memory writes.
26.6.25.1 CHI LRAM Error Injection
The following sequence describes an error injection sequence for the CHI LRAM. This sequence includes
the setup of the error injector followed by an application triggered write access to provoke an distortion of
the memory content. When the FlexRay module is in POC:default config, there are no limitations and
impacts of error injection for the application. For error injection out of POC:default config see
Section 26.7.2, CHI LRAM Error Injection out of POC:default config.
Injector Setup:
1. FR_MCR[ECCE]:= 1;
- enable ecc functionality
2. FR_EERICE[EIE]:=I_MODE;
- configure error injection mode
3. FR_EEIAR[MID]:= 1;
- select CHI LRAM for error injection
4. FR_EEIAR[BANK]:= I_BANK;
- define the bank for error injection; I_BANK = {0,1,2,3,4,5}
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-175