PXS20RM Datasheet, PDF (1187/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Register Protection (REG_PROT)
Field
WE0
WE1
WE2
WE3
SLB0
SLB1
SLB2
SLB3
Table 40-2. SLBRn field descriptions
Write Enable Bits for Soft Lock Bits (SLB):
WE0 enables writing to SLB0
WE1 enables writing to SLB1
WE2 enables writing to SLB2
WE3 enables writing to SLB3
Description
1 Value is written to SLB
0 SLB is not modified
Soft Lock Bits for one MRn register:
SLB0 can block accesses to MR{n *4 + 0}
SLB1 can block accesses to MR{n *4 + 1}
SLB2 can block accesses to MR{n *4 + 2}
SLB3 can block accesses to MR{n *4 + 3}
1 Associated MRn byte is locked against write accesses
0 Associated MRn byte is unprotected and writeable
Table 40-3 gives some examples how SLBRn[SLB] and MRn go together.
Table 40-3. Soft lock bits vs. protected address
Soft lock bit
SLBR0[SLB0]
SLBR0[SLB1]
SLBR0[SLB2]
SLBR0[SLB3]
SLBR1[SLB0]
SLBR1[SLB1]
SLBR1[SLB2]
SLBR1[SLB3]
SLBR2[SLB0]
...
Protected address
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
MR8
...
40.3.2.4 Global configuration register (GCR)
This register is used to make global configurations related with the REG_PROT.
Offset: 0x3FFC
Access: Read Always
Supervisor write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0000000 00000000000000000000000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 40-5. Global configuration register (GCR)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
40-5