PXS20RM Datasheet, PDF (69/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Table 2-2. PXS20 memory map, ordered by module name (continued)
Start Address
Size (KB)
PCTL
number
0xFFF4_8000
16
—
0xFFE4_0000
16
48
0xFFE4_4000
16
49
0x8FF1_0000
16
—
0xFFF1_0000
16
—
0xC3FD_C000
16
87
0xC3FF_0000
16
92
0xC3FE_8000
16
90
0x8FF0_0000
16
—
0xFFF0_0000
16
—
0xC3FE_4000
16
89
0xC3FF_4000
16
93
0x8FF2_4000
16
—
0xFFF2_4000
16
—
0x00F0_0000 1024
—
0xFFE7_8000
16
62
0x8FF3_8000
16
—
0xFFF3_8000
16
—
0x4000_0000
64
—
128
—
0x5000_0000
64
—
0x8FF3_C000
16
—
0xFFF3_C000
16
—
0xC3F9_0000
16
68
0xC3FD_8000
16
86
0xC3F9_4000
16
69
0x8FF0_4000
16
—
0xFFF0_4000
16
—
Mode
Region / Module Name
LS INTC_0, INTC_1
DP INTC_0
LS/DP LINFlexD_0
LS/DP LINFlexD_1
DP MPU_1
LS MPU_0, MPU_1
DP MPU_0
LS/DP Mode entry module (MC_ME)
LS/DP Periodic interrupt timer (PIT)
LS/DP Power control unit (MC_PCU)
DP PBRIDGE_1
LS PBRIDGE_0, PBRIDGE_1
DP PBRIDGE_0
LS/DP Reset generation module (MC_RGM)
LS/DP Self-test control unit (STCU)
DP Semaphores (SEMA4_1)
DP Semaphores (SEMA4_0)
LS/DP Shadow block
LS/DP Sine wave generator (SWG)
DP SWT_1
LS SWT_0, SWT_1
DP SWT_0
DP SRAM
LS SRAM
DP SRAM³
DP STM_1
LS STM_0, STM_1
DP STM_0
LS/DP System integration unit lite (SIUL)
LS/DP System status and configuration module (SSCM)
LS/DP Wakeup unit (WKPU)
DP XBAR_1
LS XBAR_0, XBAR_1
DP XBAR_0
Memory Map
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
2-5