PXS20RM Datasheet, PDF (457/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
This bit is set when the watchdog times out by counting down to zero. The watchdog must be enabled
for time-out to occur and channel 0 must be in quadrature decode count mode (CNTMODE = 100).
This bit is cleared by writing a 1 to this bit position after either writing a non-zero value to WDTOL
and/or WDTOH or exiting quadrature decode counting mode. This bit is only in channel 0.
RCF - Redundant Channel Flag
This bit is set when there is a miscompare between this channel’s OFLAG value and the OFLAG value
of the corresponding redundant channel. Corresponding channels are grouped together in the
following pairs: 0 and 1, 2 and 3, or 4 and 5. This bit can only be set if the RDNT bit is set. This bit
is cleared by writing a 1 to this bit position. This bit is only in even channels (0, 2, and 4).
ICF2 - Input Capture 2 Flag
This bit is set when an input capture event (as defined by CPT2MODE) occurs while the counter is
enabled and the word count of the CAPT2 FIFO exceeds the value of the CFWM field. This bit is
cleared by writing a one to this bit position if ICF2DE is clear (no DMA) or it is cleared automatically
by the DMA access if ICF2DE is set (DMA).
ICF1 - Input Capture 1 Flag
This bit is set when an input capture event (as defined by CPT1MODE) occurs while the counter is
enabled and the word count of the CAPT1 FIFO exceeds the value of the CFWM field. This bit is
cleared by writing a one to this bit position if ICF1DE is clear (no DMA) or it is cleared automatically
by the DMA access if ICF1DE is set (DMA).
IEHF - Input Edge High Flag
This bit is set when a positive input transition occurs (on an input selected by SECSRC) while the
counter is enabled. This bit is cleared by writing a one to this bit position.
IELF - Input Edge Low Flag
This bit is set when a negative input transition occurs (on an input selected by SECSRC) while the
counter is enabled. This bit is cleared by writing a one to this bit position.
TOF - Timer Overflow Flag
This bit is set when the counter rolls over its maximum value $FFFF or $0000 (depending on count
direction). This bit is cleared by writing a one to this bit location.
TCF2 - Timer Compare 2 Flag
This bit is set when a successful compare occurs with COMP2. This bit is cleared by writing a one to
this bit location.
TCF1 - Timer Compare 1 Flag
This bit is set when a successful compare occurs with COMP1. This bit is cleared by writing a one to
this bit location.
TCF - Timer Compare Flag
This bit is set when a successful compare occurs. This bit is cleared by writing a one to this bit location.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-15