PXS20RM Datasheet, PDF (810/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
The connection between the receive FIFO control registers and the set of physical message buffers is
established by the Receive FIFO Start Index Register (FR_RFSIR), the Receive FIFO Depth and Size
Register (RFDSR), and the Receive FIFO A Read Index Register (FR_RFARIR) / Receive FIFO B Read
Index Register (FR_RFBRIR). The system memory base address SMBA is defined by the system memory
base address register selected by the FIFO address mode bit FR_MCR[FAM].
The start byte address SADR_MBHF[1] of the first message buffer header field that belongs to the receive
FIFO in the FlexRay memory area is determined according to Equation 26-5.
SADR_MBHF[1] = (10 * FR_RFSIR[SIDX]) + SMBA
Eqn. 26-5
The start byte address SADR_MBHF[n] of the last message buffer header field that belongs to the receive
FIFO in the FlexRay memory area is determined according to Equation 26-6.
SADR_MBHF[n] = (10 * (FR_RFSIR[SIDX] + RFDSR[FIFO_DEPTH])) + SMBA
NOTE
All message buffer header fields assigned to a receive FIFO must be a
contiguous region.
Eqn. 26-6
SADR_MBDF[n]
(min) RFDSR[ENTRY_SIZE] * 2 bytes
Frame Data[n]
SADR_MBDF[i]
Frame Data[i]
SADR_MBDF[1]
Frame Data[1]
Message Buffer Data Fields
SADR_MBHF[n]
+
Frame Header[n]
Data Field Offset[n] Slot Status[n]
SADR_MBHF[i]
Frame Header[i]
Data Field Offset[i] Slot Status[i]
SADR_MBHF[1]
Frame Header[1]
Data Field Offset[1] Slot Status[1]
Message Buffer Header Fields
26-98
FR_RFDSR[A]
FR_RFSIR[A]
FR_RFDSR[B]
FR_RFSIR[B]
FR_RFARIR
FR_RFBRIR
Receive FIFO Control Register
Figure 26-116. Receive FIFO Structure
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor