PXS20RM Datasheet, PDF (337/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 16-10. DSPI_CTAR0, DSPI_CTAR1 Field Descriptions in slave mode
Field
Descriptions
SLAVE_ Slave frame size. The number of bits transferred per frame is equal SLAVE_FMSZ field value plus 1.
FMSZ Minimum valid SLAVE_FMSZ field value is 3.
SLAVE_CPO Clock Polarity. The CPOL bit selects the inactive state of the Serial Communications Clock (SCK).
L
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
SLAVE_CPH Clock Phase. The CPHA bit selects which edge of SCK causes data to change and which edge
A
causes data to be captured.
0 Data is captured on the leading edge of SCK and changed on the following edge
1 Data is changed on the leading edge of SCK and captured on the following edge
SLAVE_PE Parity Enable. PE bit enables parity bit transmission and reception for the frame
(for cut2/3 0 No parity bit included/checked.
only) 1 Parity bit is transmitted instead of last data bit in frame, parity checked for received frame.
SLAVE_PP
(for cut2/3
only)
Parity Polarity. PP bit controls polarity of the parity bit transmitted and checked
0 Even Parity: number of “1” bits in the transmitted frame is even. The DSPI_SR[SPEF] bit is set if in
the received frame number of “1” bits is odd.
1 Odd Parity: number of “1” bits in the transmitted frame is odd. The DSPI_SR[SPEF] bit is set if in
the received frame number of “1” bits is even.
16.3.2.5 DSPI Status Register (DSPI_SR)
The DSPI_SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the
occurrence of events that can generate interrupt or DMA requests. Software can clear flag bits in the
DSPI_SR by writing a ‘1’ to it. Writing a ‘0’ to a flag bit has no effect. This register may not be writable
in module disable mode due to the use of power saving mechanisms.
Address: DSPI_BASE + 0x2C
Access:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0
0
0
0 RFOF 0 RFDF 0
W w1c w1c
w1c w1c
w1c
w1c
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R
W
Reset 0
17
18
19
20 21 22 23 24 25
26
27
28
29
30
31
TXCTR
TXNXTPTR
RXCTR
POPNXTPTR
0 0 0 0 0 0 00 0 0 0 0 0 0 0
Figure 16-10. DSPI Status Register (DSPI_SR) for cut1
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-17