PXS20RM Datasheet, PDF (899/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Field
2-5
IDF
6-7
ODF
9-15
NDIV
23
en_pll_sw
24-25
Frequency-Modulated Phase-Locked Loop (FMPLL)
Table 27-2. CR Field Descriptions
Description
The value of this field sets the FMPLL Input division factor as described in Table 27-3. The reset
value is set during integration.
The value of this field sets the FMPLL Output division factor as described in Table 27-4. The
reset value is set during integration.
The value of this field sets the FMPLL Loop division factor as described in Table 27-5.The reset
value is set during integration.
This bit is used to enable progressive clock switching.
0 Progressive clock switching disabled
1 Progressive clock switching enabled
Reserved
27
i_lock
28
s_lock
29
pll_fail_mask
30
pll_fail_flag
This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing
1.
This bit is an indication of whether the FMPLL has acquired lock.
0 FMPLL unlocked
1 FMPLL locked
This bit is used to mask the pll_fail output.
0 pll_fail not masked
1 pll_fail masked
This bit is asynchronously set by hardware whenever a loss of lock event occurs while FMPLL
is switched on. It is cleared by software, writing 1.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Table 27-3. Input divide ratios
IDF[3:0]
Input division factor (idf)
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Divide by 9
Divide by 10
Divide by 11
Divide by 12
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
27-3