PXS20RM Datasheet, PDF (347/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
The shifting of data between FIFO and shift registers is more dependent upon the state of the internal FSM
rather than the exact number of elapsed clock cycles. For example, TX-DATA is loaded into the shift
register whenever the “next state” of FSM is PCS-to-SCK delay stage while the current state is IDLE,
“After SCK delay,” “Delay after transfer,” or STALL.
16.4.1 Start and Stop of DSPI Transfers
The DSPI has two operating states: STOPPED and RUNNING. The states are independent of DSPI
configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are
initiated in master mode and no transfers are responded to in slave mode. The STOPPED state is also a
safe state for writing the various configuration registers of the DSPI without causing undetermined results.
In the RUNNING state serial transfers take place.
The TXRXS bit in the DSPI_SR indicates in what state the DSPI is. The bit is set if the module in
RUNNING state.
The DSPI is started (DSPI transitions to RUNNING) when all of the following conditions are true:
• DSPI_SR[EOQF] bit is clear
• SOC is not in the debug mode is or the DSPI_MCR[FRZ] bit is clear
• DSPI_MCR[HALT] bit is clear
The DSPI stops (transitions from RUNNING to STOPPED) after the current frame when any one of the
following conditions exist:
• DSPI_SR[EOQF] bit is set
• SOC in the debug mode and the DSPI_MCR[FRZ] bit is set
• DSPI_MCR[HALT] bit is set
State transitions from RUNNING to STOPPED occur on the next frame boundary if a transfer is in
progress, or immediately if no transfers are in progress.
16.4.2 Serial Peripheral Interface (SPI) Configuration
The SPI Configuration transfers data serially using a shift register and a selection of programmable
transfer attributes. The DSPI is in SPI Configuration when the DCONF field in the DSPI_MCR is 0b00.
The SPI frames can be from four to sixteen bits long. Host CPU or a DMA controller transfer the SPI data
from the external to DSPI RAM queues to a transmit First-In First-Out (TX FIFO) buffer. The received
data is stored in entries in the Receive FIFO (RX FIFO) buffer. Host CPU or the DMA controller transfer
the received data from the RX FIFO to memory external to the DSPI. The FIFO buffers operation is
described in Section 16.4.2.4, Transmit First In First Out (TX FIFO) Buffering Mechanism, and
Section 16.4.2.5, Receive First In First Out (RX FIFO) Buffering Mechanism. The interrupt and DMA
request conditions are described in Section 16.4.6, Interrupts/DMA Requests.
The SPI Configuration supports two block-specific modes - master mode and slave mode. The FIFO
operations are similar for both modes. The main difference is that in master mode the DSPI initiates and
controls the transfer according to the fields in the SPI command field of the TX FIFO entry. In slave mode
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-27