PXS20RM Datasheet, PDF (1317/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

System Integration Unit Lite (SIUL)
47.3 Features
The System Integration Unit Lite supports these distinctive features:
• GPIO
— 121 pins which are user-configurable inputs and/or outputs
— 22 pins have user-configurable General Purpose Input (GPI) functionality
— 99 pins have user-configurable General Purpose Input/Ouput (GPIO) functionality
— Dedicated input and output registers for each GPIO pin
• External interrupts
— 4 system interrupt vectors for 32 interrupt sources
— 32 programmable digital glitch filters
— Independent interrupt mask
— Edge detection
• System configuration
— Pad configuration control
47.3.1 Register protection
The individual registers of System Integration Unit Lite are protected from accidental writes, see
Chapter 40, Register Protection (REG_PROT).
47.4 External signal description
The pad configuration allows flexible, centralized control of the pin electrical characteristics of the MCU
with the GPIO control providing centralized general purpose I/O for an MCU that multiplexes GPIO with
other signals at the I/O pads. These other signals, or alternate functions, will normally be the peripherals
functions. The internal multiplexing allows user selection of the input to chip-level signal multiplexors.
Each GPIO port communicates via 16 I/O channels. In order to use the pad as a GPIO, the corresponding
Pad Configuration Registers (PCR) for all pads used in the port must be configured as GPIO rather than
as the alternate pad function.
Table 47-1 lists the external pins used by the SIUL.
(
Table 47-1. SIUL signal properties
Name
I/O
Type
System Configuration
GPIO
I/O
External Interrupt
EIRQ[0:8, 10:18, 22, 30:31, 35:38, 77:81, 96:97]
Input
Function
General-Purpose I/O
External Interrupt Request Input
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
47-3