PXS20RM Datasheet, PDF (207/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
The burst mode and interleaved mode are not applicable to the S algorithm that can be executed only as
an atomic conversion.
When the FULL algorithm is enabled the ctu will execute an S algorithm followed by an RC algorithm
and a C algorithm.
The enabling of the trigger configured for the ADC self-testing can be performed according to the
following schemes:
• Triggered mode: according to the current CTU implementation
• Sequential mode: according to the current CTU implementation
9.4.11.4 Abort and abort chain for self testing channel
Setting MCR[ABORT] during self test channel has no effect.
In One Shot Mode, if MCR[ABORTCHAIN] is set when test channel conversion is ongoing, the test
channel is aborted and ECH is set. In this case, EOC for test channel is not generated.
For zero baud rate in Scan Mode, if MCR[ABORTCHAIN] bit is set when test channel STEP N is ongoing,
the test channel STEP N is aborted and next chain conversion starts. At the end of this chain, STEP N
conversion is performed again. (In case of Algorithm S, full algorithm is executed again).
The case of non-zero baud rate is described in Section 9.4.11.7.1, Abort chain when baud rate is non-zero.
9.4.11.5 Self test analog watchdog
The ADC also provides a monitor (watchdog) for the values returned by its analog portion for Self Test
algorithms. The analog watchdogs are used to determine whether the result of conversion for self test
algorithms lie in a particular guard area. For this purpose, seperate Self test analog watchdog registers have
been provided for each algorithm.
After the conversion of each Step of an algorithm, a comparison is performed between the converted value
and the threshold values if Analog watchdog feature is enabled by setting STAWxR.AWDE bit. If the
converted value does not lie between the upper and lower threshold values specified by Analog Watchdog
Register of the particular algorithm, corresponding error bit STSR1.ERR_x is set and Step Number in
which error occurred is updated in STSR1.STEP_x (in case of C or RC algorithm). Also, erroneous data
is written in STSR4.DATAx field. The STSR1.ERR_x bits will generate an interrupt if enabled by
corresponding Mask bit in STCR2 register. The fault indication is also given to FCCU via CF and NCF,
so that necessary action can be taken at SOC level.
Analog Watchdog feature works differently in case of Algorithm S. As already mentioned, Algorithm S is
always an atomic operation. So, seperate error bits are provided in STSR1 for each STEP of Algorithm S
to avoid overwrite in case error occurs in more than one STEP. Hence, there are seperate Mask bit for each
step in STCR1. For the same reason, seperate fields exist in Status registers (STSR2 and STSR3) to store
erroneous data for each step.
For Algorithm S STEP1, a fixed point division has to be performed outside ADC analog hardmacro (it
takes around 26 cycles after EOC for STEP1 to get divided value) and it is the divided value on which
analog watchdog checks are applied. So, the value to be compared for STEP1 contains integer as well as
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-49