PXS20RM Datasheet, PDF (631/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
At the first opportunity window on the CAN bus, the message on the SMB is transmitted according to the
CAN protocol rules. FlexCAN transmits up to eight data bytes, even if the DLC (Data Length Code) value
is bigger.
24.4.4 Receive Process
To be able to receive CAN frames into the mailbox MBs, the CPU must prepare one or more Message
Buffers for reception by executing the following steps:
• If the MB has a pending transmission, write an ABORT code (‘1001’) to the Code field of the
Control and Status word to request an abortion of the transmission, then read back the Code field
and the IFLAG register to check if the transmission was aborted (see Section 24.4.6.1,
Transmission Abort Mechanism). If backwards compatibility is desired (AEN in MCR negated),
just write ‘1000’ to the Code field to inactivate the MB, but then the pending frame may be
transmitted without notification (see Section 24.4.6.2, Message Buffer Deactivation). If the MB
already programmed as a receiver, just write ‘0000’ to the Code field of the Control and Status
word to keep the MB inactive.
• Write the ID word
• Write ‘0100’ to the Code field of the Control and Status word to activate the MB
Once the MB is activated in the third step, it will be able to receive frames that match the programmed ID.
At the end of a successful reception, the MB is updated by the MBM as follows:
• The value of the Free Running Timer is written into the Time Stamp field
• The received ID, Data (8 bytes at most) and Length fields are stored
• The Code field in the Control and Status word is updated (see Table 24-4 and Table 24-5 in
Section 24.3.2, Message Buffer Structure)
• A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the
corresponding Interrupt Mask Register bit
Upon receiving the MB interrupt, the CPU should service the received frame using the following
procedure:
• Read the Control and Status word (mandatory – activates an internal lock for this buffer)
• Read the ID field (optional – needed only if a mask was used)
• Read the Data field
• Read the Free Running Timer (optional – releases the internal lock)
Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the CPU should
defer the access to the MB until this bit is negated. Reading the Free Running Timer is not mandatory. If
not executed the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a
single MB is locked at a time. The only mandatory CPU read operation is the one on the Control and Status
word to assure data coherency (see Section 24.4.6, Data Coherence).
The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the
IFLAG Registers and not by the Code field of that MB. Polling the Code field does not work because once
a frame was received and the CPU services the MB (by reading the C/S word followed by unlocking the
MB), the Code field will not return to EMPTY. It will remain FULL, as explained in Table 24-4. If the CPU
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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