PXS20RM Datasheet, PDF (1274/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Self-Test Control Unit (STCU)
Address: Base + 0x0048
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
MBE MBE MBE
34 33 32
000000000000000
Figure 42-15. STCU MBIST End Flag High Register (STCU_MBEH)
Table 42-12. STCU_MBEH field descriptions
Field
Bits 0:28
Bits 29:31
Description
Reserved
These are reserved bits. These bits are always read as ‘0’ and must always be written with ‘0’.
MBEx: MBIST End status
0: MBIST execution is not finished.
1: MBIST execution is finished.
NOTE
A BIST counts as successfull when no fault was detected during execution
(see MBSL, MBSH) and its execution is finished (see MBEL, MBEH).
42.4.3.11 STCU LBIST MISR Expected Low Register (STCU_LB_MISREL) [cut2/3
only]
The STCU_LB_MISREL register defines the LSB part of the Expected MISR of each LBIST controller.
Address: Base + 0x0088 + (n × 0x20)¹ [cut2/3 only]
Access: User read
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
MISREL[31:16]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MISREL[15:0]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 42-16. STCU LBIST MISR Expected Low Register (STCU_LB_MISREL) [cut2/3 only]
NOTES:
1 _{The n variable represents the repeated register blocks of the multiple LBISTs: n ranges from 0 up to 2.}
42-16
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor